Transistor circuit

ABSTRACT

A lateral region detects the saturation condition and provides overflow negative feedback or a trigger preparation voltage.

United States Patent [1 1 Ruegg TRANSISTOR CIRCUIT [75] Inventor: HeinzWalter Ruegg, Hausena,

Switzerland [73] Assignee: U.S. Philips Corporation, New

York, NY.

[22] Filed: Nov. 21, 1973 [21] Appl. No.: 418,210

Related U.S. Application Data I [63] Continuation of Ser. No. 189,086,Oct. [4, 1971,

abandoned.

[30] Foreign Application Priority Data Oct. 23, 1970 Netherlands 7015520[52] U.S. Cl. 357/40; 357/35; 357/48; 357/37; 307/237; 307/303 [51] Int.Cl. H01] 19/00 [58] Field of Search 317/235 Y, 235 D, 235 E, 317/235 AA;307/237, 303; 357/35, 40, 48, 37

[56] References Cited UNITED STATES PATENTS 3,482,l 11 12/1969 Gundersonet al. 307/237 [45] June 17, 1975 OTHER PUBLICATIONS Reap 3l7/235 Breweret al. 317/235 C. Cook et al., New Semiconductor Networks Reduce SystemComplexity," Electronics, Jan. 10, 1964, pp. 25-29.

T. Collins, Transistor-Collector Clamp, I.B.M. Tech. Discl. Bull., Vol.10, No. '2, July, 1967, p. 180.

Electronics, Apr. 3, l967, p. 44.

Primary ExaminerAndrew 1. James Assistant Examiner-Joseph E. Clawson,Jr.

Attorney, Agent, or FirmFrank R. Trifari; Ronald L. Drumheller [5 7]ABSTRACT A lateral region detects the saturation condition and providesoverflow negative feedback or a trigger preparation voltage.

5 Claims, 5 Drawing Figures PATENTEDJUN 17 I975 SHEET Fig.2a

INVENTOR.

HEINZ W.RUEGG AGENT PATENTEDJUN 17 I975 I3 ,634

INVENTOR." HEINZ W.RUEGG AGENT TRANSISTOR CIRCUIT This is a continuationof application Ser. No. 189,086, filed Oct. 14, 1971, and now abandoned.

The invention relates to a transistor circuit including means fordetecting the saturation condition of a transistor. In a known circuit,as soon as the base-collector junction of the transistor is operated inthe forward direction, a second transistor is rendered conductive sothat a current becomes available. This current may be used, for example,for further driving of the first transistor so as to prevent excessivecharge storage in its base. Another use consists in that this current,of the corresponding voltage, is used for sensitive conditioning of atrigger circuit, as will be set out more fully hereinafter. The termsaturation is used in this connection to mean that the first transistorbecomes so highly conductive that the collector injects charges into thebase and vice versa.

The circuit according to the invention is particularly suitable forconstruction as an integrated circuit. In this case it is of importancethat the use of circuit elements which occupy much space should beavoided as far as possible. Hence, the use of inductance in theintegrated circuit element is out of the question, whilst the number ofcapacitors and resistors should be restricted to a minimum. This alsoensures that the circuit is suitable for very high frequencies and maybe operated with pulses of very short duration. Such a property is ofgreat advantage in logic circuits.

The invention is characterized in that laterally of a region surroundedby the collector-base junction of the (first) transistor a furtherregion of the same conductivity type is provided which forms thecollector region of a (second) lateral transistor the emitter-basejunction of which corresponds to the base-collector junction of thefirst transistor, and in that during the saturation of the firsttransistor charges collected by the collector of the second transistorare supplied to an impedance across which a voltage is produced whichdepends upon the saturation condition of the first transistor.

In a preferred embodiment of the invention there is provided near thebase region of a first transversal transistor constructed according tothe integrated circuit technology the further region of the sameconductivity type as this base region, which further region is separatedfrom this base region by the collector region of the transversaltransistor in a manner such that the lateral (second) transistor of aconductivity type opposite to that of the transversal (first) transistoris obtained, the collector of this lateral transistor being constitutedby the further region, charges collected by this collector beingsupplied to the impedance across which a voltage depending upon thesaturation condition is produced.

This impedance preferably takes the form of the base-emitter path of athird transistor to the input electrode of which more remote from thecollector of the second transistor the same potential is applied as tothe emitter of the first-mentioned transistor. This ensures that at theoccurrence of the saturation of the first transistor the voltageproduced at the collector of the second transistor has just the rightvalue to drive the base of the third transistor without the need foradditional circuit elements. Obviously, a resistor and/or a furtheramplifier may be included in the connection between the collector of thesecond transistor and the base of the third transistor, but as a rulesuch circuit elements can be dispensed with so that a single connectionis sufficient. Thus a very simple and effective circuit is pro ducedwhich may readily be manufactured in integrated circuit form.

Another embodiment is characterized in that in a transistor circuitincluding means for determining the saturation of a first transistor thebase-collector path of which is shunted by the emitter-base path of asecond transistor a third transistor is provided, the collector of thesecond transistor being connected to an input electrode (the base or theemitter) of the third transistor, the other input electrode (the emitteror the base) of which is at substantially the same potential as theemitter of the first transistor.

It is known to provide near the base region of a first transversaltransistor a further region so that a second lateral transistor of theopposite conductivity type is formed. However, this further regionusually has a voltage applied to it such that it acts as the emitter ofthe second transistor. In contradistinction thereto, in the circuitaccording to the invention a further region is biased so that it isoperated as a collector and only delivers a corresponding voltage aftersaturation.

Embodiments of the invention will now be described, by way of example,with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 is a schematic circuit diagram of an amplifier according to theinvention,

FIG. 2 is a sectional view and a top plan view (FIG. 2a) of thecorresponding integrated semiconductor element,

FIG. 3 is another circuit diagram in which the principle of theinvention is used, and

FIG. 4 shows the circuit element of FIG. 3 in integrated-circuit form.

Referring now to FIG. 1, there is shown a first transistor T of the NPNtype. The emitter of this transistor is, for example, at earthpotential; to its base an input voltage V,- is applied and from itscollector an amplified signal, for example, an amplified voltage V setup across a load resistor R, is derived. With increasing input voltageV,- the voltage at the collector of the transistor T decreases until avalue about equal to the value of the emitter potential (earthpotential) has been reached. At so low a collector voltage the voltageat the base of the transistor T, becomes more positive than itscollector voltage, so that the collector-base junction is operated inthe forward direction and the collector starts injecting charges intothe base, and vice versa.

It is an object of the invention to detect this saturation condition, toeliminate the inconvenient consequences thereof and to use the voltagevariation resulting from this detection for further adjustments of thecircuit. In particular, excessive charge storage in the base is avoidedand the trigger circuit may sensitively be put into a state ofreadiness.

FIG. 2 shows the construction of a semiconductor element according tothe invention. By conventional integrated-circuit techniques an N-typeisland provided with a collector contact 0, is formed in a P-typesubstratepInto this island P-type regions provided with a base contact band a collector contact c respectively are simultaneously diffused sonear one another that a lateral PNP effect is obtainable. (For thispurpose the spacing must be smaller than the diffusion length of theminority carriers i.e., the holes in the N-type region which separatesthe P-type regions.) Furthermore an N -type region provided with anemitter contact 2, is formed in one of the P-type regions.

The n, p and n regions connected to the contacts e,, b, and 0, form atransversal transistor which corresponds to the transistor T, of FIG. 1.The p, n and p regions connected to the contacts 12,, c, and form theabove-described lateral transistor which corresponds to the transistor Tof FIG. 1. The contact is connected to earth through an impedance Z,which in FIG. 1 is constituted by the base-emitter path of thetransistor T Owing to this connection 0, will act as the collector, b,as the emitter and c, as the base of this lateral transistor.

When an increasing positive voltage V,- is applied to the contactb, (anegative voltage V,- would have no effeet at all, since in this case allthe PN junctions would be blocked), the voltage V at the contact c,gradually decreases from +B (the supply voltage) to earth potential. Aslong as V,- is less positive than V,,, the PN junction between theregions connected to the contacts b, and c, is operated in the reversedirection and hence the lateral pnp transistor (T in FIG. 1) remains cutoff. When, however, V, becomes more positive than V (commencement of thesaturation of T,), the p-type region connected to b, starts injectingholes into the 11- type region connected to c,, which are collected bythe adjacent p-type region connected to c because just this region thenis at a negative voltage relative to V,-.

Such an effect may also be produced if the transistor T were located ina separate island, its emitter-base path shunting the basewollector pathof the transistor T,. Not only would this require more space, but alsothe topology shown in FIG. 2 has the large advantage that immediately atthe location at which the collector-base junction of the transversaltransistor starts injecting i.e., the point at which saturation occursthe p-type region connected to c collects part of these injectedcarriers, so that the voltage variation at the contact 6 can further beutilised, for the current flows from +B through R and 0,, then passesthrough the transversal transistor and subsequently flows from e, toearth; hence the voltage at c, is more positive than the voltage in theN-type collector region in the immediate proximity of the collector-basejunction, so that this junction may already be in the injection rangebefore the voltage at the contact 0, has dropped below the voltage atthe contact b,.

In practice the transversal npn transistor will be fully saturated at aninput voltage V,- of about +0.6 volt. The voltage at the collectorcontact c, will then have dropped to only a few tenths of a millivolt.The lateral pnp transistor is conductive and the voltage at the contactC, will remain a few tenths of a millivolt below the input voltage V,-0.6 volt). This voltage has exactly the correct value to renderconductive the transistor T of FIG. 1 which is connected in parallelwith the signal source. As a result, a heavier load is imposed upon theinput signal source, which has a high internal resistance, and thevoltage V,- does not rise further, but to the base of the transistor T,only so much current is supplied as is required for the saturationcondition. Thus, excessive charge storage in the base region of thetransistor T, is avoided, so that the speed of the circuit arrangementwhen operated with pulse signals is increased. This is the reason whythe p-type region connected to c, is provided opposite only part of thep-type region connected to b,, so that it has only a low internalcapacitance. This region may even be surrounded (for example partly) bythe p-type region connected to b,, as is shown in the plan view of FIG.2a, to obtain a high inverse base-collector current gain factor of thelateral pnp transistor.

To compensate for the aforementioned loss of a few tenths of a millivoltthe transistor T may be given an emitter surface area larger than thatof the transistor T,, so that T is rendered conductive at a lower basevoltage than is T,. Alternatively, there may be included in the emittersupply lead r of the transistor T, a resistor which occupiescomparatively little space, so that the voltage V, must be increased bythe voltage drop across this resistor (for example of the order ofmagnitude of 50 millivolts) before saturation of the transistor T,occurs. Because the emitter of the transistor T is directly connected toearth, however, this also ensures that T becomes conductive as soon as Tstarts conducting and hence saturation of T, occurs. Owing to the largeoverall amplification of the transistors T and T however, these stepsare not absolutely necessary.

The embodiment shown in FIG. 3 shows the use of the principle accordingto the invention for putting a flip-flop circuit into a state ofreadiness for changing its condition. The flip-flop circuit comprisestwo npn transistors T, and T, the collector and base electrodes of whichare cross-coupled. As has been described with reference to FIGS. 1 and2, the sole provision of the ptype region connected to c gives rise tothe formation of a lateral transistor T the collector of which isconstituted by this p-type region. In FIG. 3 also, the lateraltransistor associated with the transversal transistor T, is denoted by Tthe lateral transistor similarly associated with the transversaltransistor T, is denoted by T The collector of these transistors,however, are connected to the bases of two further transistors T, and Trespectively the emitter-collector paths of which are connected inparallel with those of the transistors T, and T, respectively.

It is assumed that in one stable condition of the flipflop circuit thetransistor T is conducting. A current source I will then produce avoltage of about 0.6 volt at its base, with consequent saturation. Ashas been described hereinbefore, a substantially equal voltage will thenbe produced at the collector of the transistor T,, which voltage istransferred to the base of the transistor T Hence, the base of thetransistor T, is at a voltage of about 0.6 volt and that of thetransistor T, is at about 0 volt. A positive trigger pulse V,- of onlyfrom 0.1 to 0.2 volt when applied to these two bases causes thetransistor T, to become highly conducting, whilst the transistor T isnot yet conducting, so that the voltage at the base of the transistor T,will become 0 volt. As a result, T, and T are cut off and the supplysource I causes the transistor T, to become conducting (T, cannotconduct in the reverse direction, because the collector-base junction ofT 2 remains cut off owing to the supply voltage +B Which is made greaterthan 0.6 volt). After the trigger pulse V,- has disappeared, thecollector voltage of T i.e., the base voltage of T.,', drops to 0 volt,T is cut off and the flip-flop circuit remains in the opposite statewith T, cut off and T, conducting.

Because in this manner a voltage corresponding to the occurrence ofsaturation of the transistor T, is produced at the base of thetransistor T the flip-flop circuit is put into a state of readiness suchthat a very small input pulse suffices to cause it to change state.Obviously, this effect will be obtained irrespective of the fact whetherthe transistor T is already conducting in the rest condition, i.e.,irrespective of the fact whether the negative feedback of the base driveof the transistor T, has already commenced. Therefore, theabove-described steps to shift this starting point (increased emittersurface area of T or of T and/or the inclusion of resistors in theemitter supply leads of T or T are not absolutely necessary.

When trigger pulses of, say, at least 0.6 volt are used, there is a riskthat not only the transistor T becomes highly conducting, but that alsothe transistor T, becomes conducting, which would adversely affect thereliability of the change of state of the flip-flop circuit. Toeliminate this risk the base of T (and T is connected to a furtherregion of the transistor T (T respectively) which in the semiconductorelement shown in FIG. 2 takes the form of a further N -type region,which is located beside the n -type region connected to e and with thisregion forms a lateral npn transistor T and hence is indicated in FIG. 3by an emitter symbol, although this further region has the function of acollector, as will be explained hereinafter.

In the rest condition, in which T is conducting and T, is cut off, thevoltage at the base of T is volt, as was set out hereinbefore. Becausethe base-emitter path common to the transistor T and the transistor T isconducting (owing to the saturation of the transistor T electrons arealso injected into the base of this transistor by its collector, andthese electrons reach the collector of the transistor T the base voltageof T cannot become positive for this reason also. This condition doesnot change when the input pulse V,- is received, as long as thetransistor T still is conducting. When, however, the transistor T is cutoff owing to the fact that the transistor T becomes conducting, theflip-flop circuit changes state and causes a positive voltage to beproduced at the base of the transistor T, by the collector of thetransistor T and by V,-. At the same time, the transistor T becomesconducting and discharges a capacitance connected between its emitterand the V,- terminal. Instead of two diodes D and D which act ascapacitances (the capacitors shown in FIG. 3 form part of the equivalentcircuit diagrams of these diodes) the pulse V,- may also be appliedthrough resistors to the bases of the transistors T and T in which eventthe source which supplies the voltage V,- is less heavily loaded.Alternatively, this source may take the form of a transistor having twocollectors, one collector being connected to the connection between thecollector of T and the base of T, and the other being connected to theconnection between the collector T and the base of T.,'.

FIG. 4 shows the topology of the semiconductor element shown in FIG. 3.The element contains four islands which are separated from one anotherby P-type island diffusion (dotdash lines). The collector regions of thetransistors T T and T T respectively, which are provided with buriedlayers, fill the island areas at the left-hand and the right-hand sidesrespectively of the upper part. The lower part contains the diodes (Dand D in FIG. 3) to which the input signal is applied by way of thecontact area of V,-.

The anodes of these diodes are connected through openings w and w to acontacting strip shown by shading which contacts the collector c (and cof the transistor T (and T respectively), the base b (and b,) of thetransistor T (and T, respectively) and the collector c (and c of thetransistor T (and T respectively). The transistors T T T and T arelocated in the island at the upper left, whilst the transistors T T Tand T are located in the island at the upper right. The emitter e (e,')of the transistor T (T respectively) is connected to the islanddiffusion region through the opening W (w Similarly, the emitter e,(e,') of the transistor T (T respectively) is connected to the islanddiffusion region through the opening W (w,,). The base b (b is connectedto the collector region c, (c, respectively) which is also connected tothe output contact area V (V The p-type doped regions are indicated bybroken lines. The current sources connected to V (and V respectively)generally are the collector-emitter paths of lateral PNP transistors. Aswill be seen from the Figure, the collector regions associated with 0(and 0 respectively) have been provided as comparatively small diffusionregions near the base .regions associated with b, (and b and each form,to-

gether with the respective base region and the intermediate collectorregion, a lateral PNP transistor. The n*- type regions associated with eand 0 together with the base region associated with b, form a lateralNPN transistor, and owing to the small size thereof, to the largediffusion length of the minority carriers and to the charges which bythe injection of electrons from the collector into the base of the firsttransistor reach the collector c the current gain is high enough toachieve the effects described with reference to FIG. 3. If desired, theregions associated with e and a may be adjacent to one another.

Obviously, many further modifications are possible. The currentgenerated at the collector c (or 0 may be supplied to the emitter of afurther PNP transistor the base of which is earthed, and then be furtherutilized. The locations and sizes of the various regions of FIG. 4 maybe altered without the desired effects being adversely affected. Thedopings may be reversed, i.e., transversal PNP and lateral NPNtransistors may be used. Also, complementary transversal andcomplementary lateral transistors may be provided on a semiconductorelement. Furthermore, the first transistor T may be a lateral transistor(for example a lateral PNP transistor), whilst the further (P-type)region which forms the collector of the transistor T may be provided inthe (N-type) base island laterally of the (P-type) collector region ofthe transistor T In this case care should be taken to ensure that the(hole) charges injected into the base of the transistor T by the emitterdo not immediately reach the further region, for example by designingthe (P-type) collector region of the first transistor as an annular(P-type) region surrounding its (P-type) emitter region, so that thisfurther region collects (hole) charges only when the collector of thefirst transistor owing to saturation injects (hole) charges into itsbase, which reach the further region. It will be appreciated that thismutual decoupling between the emitter of the first transistor and thecollector of the second transistor automatically occurs in the examplesshown in FIGS. 2 and 4.

What is claimed is:

1. A solid state device comprising:

a first region of semiconductor material of one semiconductor type;

second and third regions of semiconductor material a fourth region ofsemiconductor material of said one semiconductor type forming anisolated island within said third region, whereby said fourth reg-ionacts as the emitter region of a transversal transistor, said third andfirst regions respectively acting as the base and collector thereof;

further transistor having a base of semiconductor material of saidopposite semiconductor type and an emitter and collector ofsemiconductor material of said one semiconductor type, said base,emitter and collector being electrically connected to said second,fourth and third regions respectively, whereby said lateral transistoris conductive only when said transversal transistor is actuallysaturated and thereby causes said further transistor to limit saturationof said transversal transistor in response thereto; and

means for making electrical connection to said third and fourth regionsand to said first region at a location remote from said portion thereofspacing said second and third regions.

2. The solid state device of claim 1 wherein said one semiconductor typeis N type and said opposite semiconductor type is P type.

3. The solid state device of claim 1 wherein said third region at leastpartly surrounds said second region.

4. The solid state device of claim 1 further comprising 'a substratesupporting said first region, said substrate being composed ofsemiconductor material of said opposite semiconductor type.

5. The solid state device of claim 1 wherein the emitter surface area ofsaid further transistor is larger than the effective emitter surfacearea formed between said third and fourth regions.

UNITED STATES PATENT AND TRADEMARK OFFICE CETIFICATE OF CORRECTIONPATENTNO. 3,890,634

DATED June 17, 1975 INVENTORB) I HEINZ WALTER RUEGG It is certified thaterror appears in the above-identified patent and that said LettersPatent are hereby corrected as shown below:

IN THE SPECIFICATION Column 4, line 60, "Which" should be --which-;

Column 6, line 9, "T should be T line 12, "W should be -w Signed andScaled this twenty-fifth Day of May 1976 [SEAL] A He: r.-

RUTH C. MASON C. MARSHALL DANN Artestmg Officer Commissioner of Parentsand Trademarks

1. A solid state device comprising: a first region of semiconductormaterial of one semiconductor type; second and third regions ofsemiconductor material of the opposite semiconductor type formingmutually isolated islands within said first region, said second regionbeing closely spaced from only a portion of the surface area of saidthird region by a portion of said first region, said portion of saidfirst region having a width less than the diffusion length of minoritycarriers in said first region, whereby said portion of said first regionacts substantially as the base region of a lateral transistor, saidsecond and third regions respectively acting as the collector andemitter thereof; a fourth region of semiconductor material of said onesemiconductor type forming an isolated island within said third region,whereby said fourth region acts as the emitter region of a transversaltransistor, said third and first regions respectively acting as the baseand collector thereof; a further transistor having a base ofsemiconductor material of said opposite semiconductor type and anemitter and collector of semiconductor material of said onesemiconductor type, said base, emitter and collector being electricallyconnected to said second, fourth and third regions respectively, wherebysaid lateral transistor is conductive only when said transversaltransistor is actually saturated and thereby causes said furthertransistor to limit saturation of said transversal transistor inresponse thereto; and means for making electrical connection to saidthird and fourth regions and to said first region at a location remotefrom said portion thereof spacing said second and third regions.
 2. Thesolid state device of claim 1 wherein said one semiconductor type is Ntype and said opposite semiconductor type is P type.
 3. The solid statedevice of claim 1 wherein said third region at least partly surroundssaid second region.
 4. The solid state device of claim 1 furthercomprising a substrate supporting said first region, said substratebeing composed of semiconductor material of said opposite semiconductortype.
 5. The solid state device of claim 1 wherein the emitter surfacearea of said further transistor is larger than the effective emittersurface area formed between said third and fourth regions.